1. Field of the Invention
The present invention generally relates to a semiconductor storage device and, more particularly, to a semiconductor storage device which conducts a late-write operation.
2. Description of the Related Art
Some semiconductor storage devices conduct a late-write operation so as to provide a timing margin in writing data. In the late-write operation, when a command to write particular data is input, the data is not immediately written to a memory cell in a core circuit, but is retained in an internal buffer. Thereafter, when a command to write following data is input, the first data is written to the memory cell in the core circuit for the first time. The above-mentioned following data is stored in the internal buffer, and is retained therein until a further next write-command is input.
Since there are plenty of steps between inputting data and writing the data to the core circuit, it takes a long time to finish writing the data to the core circuit in one operation. The semiconductor storage device conducting the late-write operation writes the data only in the internal buffer in a first operation. Therefore, it only takes a short time to finish the data writing in one operation, providing a sufficient timing margin in the data writing.
The semiconductor storage device conducting the late-write operation requires a contrivance when reading data written last. That is, since data written last is stored in the internal buffer, the data needs to be written out, not from an address in the core circuit corresponding to this data, but from the internal buffer in which the data is stored.
To realize this contrivance, the semiconductor storage device conducting the late-write operation needs to compare a present read address with a write address input last. Thereby, when the present read address and the write address input last match each other, the data is written out, not from the core circuit, but from the internal buffer. This enables reading data written by a preceding write operation.
However, in a test operation, the semiconductor storage device having the above-described structure conducting the late-write operation may result in writing data to or reading data from the internal buffer instead of writing data to or reading data from a memory cell aimed in the test. In this case, it is impossible to confirm operations of the memory cell, let alone to reject the memory cell if it is an inferior cell.
Further, in a test operation, the semiconductor storage device having the above-described structure conducting the late-write operation has to be given a same write-command twice to surely write input data to the core circuit. A second write-command ensures writing the data corresponding to a first write-command to the core circuit. In this course, data corresponding to the second write-command is stored in the internal buffer, and, when another write-command is input, this data corresponding to the second write-command is written to the core circuit. As a result, the same data is written to the same memory cell.
When same data is written twice to the same memory cell in a test operation, an excess electric charge is applied also to an inferior memory cell that would normally be rejected as lacking a restoration. As a result, the memory cell is not detected out as an inferior cell lacking a restoration. This hinders effective rejection of inferior memory cells.
It is a general object of the present invention to provide an improved and useful semiconductor storage device in which device the above-mentioned problems are eliminated.
A more specific object of the present invention is to provide a semiconductor storage device which device can effectively detect an inferior memory cell in a test operation.
In order to achieve the above-mentioned objects, there is provided according to one aspect of the present invention a semiconductor storage device conducting a late-write operation, the device comprising:
a memory core circuit storing data;
a data latch circuit storing preceding data corresponding to a preceding write-operation;
an address compare circuit comparing a preceding address corresponding to the preceding write-operation and a present address corresponding to a present read-operation so as to determine whether the preceding address and the present address match each other; and
a control circuit controlling a test read-operation to read data from the memory core circuit regardless of whether the preceding address and the present address match each other.
Additionally, in the semiconductor storage device according to the present invention, the control circuit controls a normal read-operation to read data from the memory core circuit when the preceding address and the present address do not match each other, and controls a normal read-operation to read the preceding data from the data latch circuit when the preceding address and the present address match each other.
Additionally, the semiconductor storage device according to the present invention further comprises:
a read-data amplifier amplifying data read from the memory core circuit; and
a data input-output buffer outputting the data amplified by the read-data amplifier out of the semiconductor storage device,
wherein the control circuit deactivating the read-data amplifier when the preceding address and the present address match each other in a normal read-operation, and activating the read-data amplifier regardless of whether the preceding address and the present address match each other in a test read-operation.
Additionally, in the semiconductor storage device according to the present invention, the control circuit controls the data latch circuit to output the preceding data when the preceding address and the present address match each other in a normal read-operation, and the control circuit controls the data latch circuit not to output the preceding data regardless of whether the preceding address and the present address match each other in a test read-operation.
In order to achieve the above-mentioned objects, there is also provided according to another aspect of the present invention a semiconductor storage device conducting a late-write operation, the device comprising:
an address compare circuit comparing a preceding address corresponding to a preceding write-operation and a present address corresponding to a present read-operation so as to determine whether the preceding address and the present address match each other; and
a control circuit controlling a normal read-operation to read data from a memory core circuit when the preceding address and the present address do not match each other, controlling a normal read-operation to read data not from the memory core circuit but from a data latch circuit when the preceding address and the present address match each other, and controlling a test read-operation to read data from the memory core circuit regardless of whether the preceding address and the present address match each other.
According to the present invention, in a test operation, the semiconductor storage device can write data not to or read data not from an internal data buffer, but can write data to or read data from a memory cell aimed in the test. This enables confirming operations of a memory cell effectively and enables rejecting an inferior memory cell.
In order to achieve the above-mentioned objects, there is also provided according to another aspect of the present invention a semiconductor storage device having a function to mask one of higher order bits and lower order bits of all bits of data to be written in a normal write-operation, the device comprising:
a mask control circuit capable of masking all the bits of the data in a test write-operation.
Additionally, the semiconductor storage device according to the present invention conducts a late-write operation, the device further comprising:
a data latch circuit storing preceding data corresponding to a preceding write-operation;
a write-data amplifier amplifying the preceding data in a following write-operation; and
a memory core circuit storing data amplified by the write-data amplifier,
wherein the mask control circuit capable of masking all bits of data to be written to the memory core circuit.
Additionally, in the semiconductor storage device according to the present invention, the mask control circuit comprises:
a switch circuit coupling a mask control signal for masking higher order bits of the data and a mask control signal for masking lower order bits of the data so as to generate a mask control signal for masking all bits of the data;
a mask latch circuit storing the mask control signal for masking all bits in a first write-operation and outputting the mask control signal for masking all bits in a second write-operation; and
a write-data amplifier activating circuit controlling activation of the write-data amplifier according to the mask control signal for masking all bits.
According to the semiconductor storage device of the present invention, all bits of data to be written to a memory core circuit can be masked in a second write-operation so as to avoid writing a same data to a same memory cell twice. Therefore, a memory cell that is to be rejected as lacking a restoration can surely be detected as an inferior cell. Thus, an inferior memory cell can be rejected effectively in a test of a semiconductor storage device.
Other objects, features and advantages of the present invention will become more apparent from the following detailed description when read in conjunction with the accompanying drawings.